Investigation of Robust Fully-Silicided NMOSFETs for Sub-100 nm ESD Protection Circuits Design
نویسندگان
چکیده
This paper demonstrates a fully-silicided ESD protection device design in sub-100nm integrated circuits. No drain ballast resistor required is the most significant feature that makes the new device differ form the conventional ones. Accordingly, a simplified manufacturing process and a reduced device area could be obtained simultaneously. It is believed that the achievements are caused from the floating charge effects during the ESD stressed. On the other hand, in avoiding the device function affected by the floating charges, a switch is incorporated at the body electrode. The newly designed device structure is very attractive in novel ESD design for the consideration of its low cost, small size and high efficiency.
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